AD9709_15 datasheet(16/32 Pages) AD

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AD9709

Rev. B | Page 16 of 32

Timing specifications for interleaved mode are shown in Figure 28

and Figure 30.

The digital inputs are CMOS compatible with logic thresholds,

VTHRESHOLD, set to approximately half the digital positive supply

(DVDDx) or

VTHRESHOLD = DVDDx/2 (±20%)

DATA IN

IQSEL

IQWRT

IQCLK

IOUTA

IOUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

500 ps

tPD

tLPW

tH*

Figure 28. 5 V or 3.3 V Interleaved Mode Timing

At 5 V it is permissible to drive IQWRT and IQCLK together as

shown in Figure 29, but at 3.3 V the interleaved data transfer is

not reliable.

DATA IN

IQSEL

IQWRT

IQCLK

IOUTA

IOUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

tH*

tPD

tLPW

Figure 29. 5 V Only Interleaved Mode Timing

IQSEL

IQWRT

IQCLK

IQRESET

INTERLEAVED

DATA

DAC OUTPUT

PORT 1

DAC OUTPUT

PORT 2

Figure 30. Interleaved Mode Timing

The internal digital circuitry of the AD9709 is capable of operating

at a digital supply of 3.3 V or 5 V. As a result, the digital inputs

can also accommodate TTL levels when DVDD1/DVDD2 is set to

accommodate the maximum high level voltage (VOH(MAX)) of the

TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper

compatibility with most TTL logic families. Figure 31 shows the

equivalent digital input circuit for the data and clock inputs.

The sleep mode input is similar with the exception that it

contains an active pull-down circuit, thus ensuring that the

AD9709 remains enabled if this input is left disconnected.

DIGITAL

INPUT

DVDD1

Figure 31. Equivalent Digital Input

Because the AD9709 is capable of being clocked up to 125 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. Operating the AD9709

with reduced logic swings and a corresponding digital supply

(DVDD1/DVDD2) results in the lowest data feedthrough and

on-chip digital noise. The drivers of the digital data interface

circuitry should be specified to meet the minimum setup and

hold times of the AD9709 as well as its required minimum and

maximum input logic level thresholds.

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