AD9518-3_15 datasheet(9/64 Pages) AD

Nome de Peças	AD9518-3

Descrição Electrónicos	6-Output Clock Generator with Integrated 2.0 GHz VCO

PDF	64 Pages

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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9 / 64 page

Data Sheet

AD9518-3

Rev. C | Page 9 of 64

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and

VCO; uses rising edge of clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz;

Divider = 1

fs rms

BW = 12 kHz to 20 MHz

CLK = 622.08 MHz; LVPECL = 155.52 MHz;

Divider = 4

fs rms

BW = 12 kHz to 20 MHz

CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16

215

fs rms

Calculated from SNR of ADC method; DCC not used

for even divides

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5

245

fs rms

Calculated from SNR of ADC method; DCC on

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

fs rms

Calculated from SNR of ADC method

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