9

FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs

SUPPLY VOLTAGE

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs

FREQUENCY

0

5

SUPPLY VOLTAGE (VDD)

LOAD CAPACITANCE (CL) = 50pF

10

15

510

15

20

10V

5V

10V

8

6

4

2

8

6

4

2

10

SUPPLY VOLTS (VDD) = 15V

tr, tf = 20ns

8

6

4

2

8

6

4

2

INPUT FREQUENCY (fCL) (kHz)

01

1

8

6

4

2

10

8

6

4

2

8

6

4

2

8

6

4

2

CL = 15pF

CL = 50pF

Test Circuit and Waveform

FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

CL

CL

CL

CL

CL

100

µF

ID

500

µF

PULSE

GENERATOR

50%

10%

90%

20ns

VDD

20ns

VARIABLE

WIDTH

VSS

Acquisition System

FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM

16 CHANNEL

MULTIPLEXER

CD4067

SELECT

INPUTS

SAMPLE

AND

HOLD

10 BIT

A/D

CONVERTER

CONVERSION

LOGIC

Q1

Q4

CD4516BMS

AMPLI-

FIER

CLOCK

PRESET ENABLE

END

CLOCK

START

ANALOG

DATA

INPUTS

PARALLEL

DATA

OUTPUTS

PRESET

INPUTS

NOTE:

This acquisition system can be operated in the random access mode by

jamming in the channel number at the present inputs, or in the sequential

mode by clocking the CD4516BMS.

CD4510BMS, CD4516BMS