M80C186 datasheet(46/59 Pages) INTEL

46 / 59 page

M80C186

PIN TIMINGS (Continued)

AC CHARACTERISTICS

(Over Specified Operating Conditions) (Continued)

All timings are measured at 15V and 100 pF loading on CLKOUT unless otherwise noted

All output test conditions are with CL e 50–200 pF (10 MHz) and CL e 50–100 pF (125 MHz)

For AC tests input VIL e 045V and VIN e 24V except at X1 where VIH e VCC b 05V

Symbol

Parameter

M80C186-10

M80C186-12

Unit

Comments

Min

Max

Min

Max

M80C186 MASTER INTERFACE TIMING RESPONSES

(Continued)

TLLAX

Address Hold to

TCHCL b 20

TCHCL 15

50 pF – 100 pF

10 MHz

all outputs

CL e

(except TCLTMV)

50 pF – 200 pF b

125 MHz

CL e

all outputs

ALE Inactive (min)

TCLDV

Data Valid Delay

TCLDOX

Data Hold Time

TWHDX

Data Hold after WR (min)

TCLCL b 34

TCLCL b 20

TCVCTV

Control Active Delay 1

TCHCTV

Control Active Delay 2

TCVCTX

Control Inactive Delay

TCVDEX

DEN Inactive Delay

(Non-Write Cycle)

TAZRL

Address Float to

RD Active

TCLRL

RD Active Delay

TCLRH

RD Inactive Delay

tRHLH

RD Inactive to ALE High

TCLCH b 14

TRHAV

RD Inactive to

TCLCL b 40

TCLCL b 20

Address Active (min)

TCLHAV

HLDA Valid Delay

TRLRH

RD Pulse Width (min)

2TCLCL b 46

2TCLCL b 40

TRVCH

RD Valid to

Clock High

TWLWH

WR Pulse Width (min)

2TCLCL b 34

2TCLCL b 30

tWHLH

WR Inactive to AEE High

TCLCH b 14

TWHDEX

WR Inactive to

TCLCH b 10

DEN Inactive

TCSVLL

Chip Select Valid

TCLCH b 14

to ALE Low

TAVLL

Address Valid to

TCLCH b 19

TCLCH b 15

ALE Low (min)

TCHSV

Status Active Delay

TCLSH

Status Inactive Delay

TCLTMV

Timer Output Delay

100 pF max

10 MHz

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