82C55A

OTHER TIMINGS

Symbol

Parameter

82C55A-2

Units

Test

Min

Max

Conditions

WR e 1 to Output

350

ns

Peripheral Data Before RD

0ns

Peripheral Data After RD

0ns

ACK Pulse Width

200

ns

STB Pulse Width

100

ns

Per Data Before STB High

20

ns

Per Data After STB High

50

ns

ACK e 0 to Output

175

ns

ACK e 1 to Output Float

20

250

ns

WR e 1toOBF e 0

150

ns

ACK e 0toOBF e 1

150

ns

STB e 0toIBF e 1

150

ns

RD e 1toIBF e 0

150

ns

RD e 0 to INTR e 0

200

ns

STB e 1 to INTR e 1

150

ns

ACK e 1 to INTR e 1

150

ns

WR e 0 to INTR e 0

200

ns

see note 1

Reset Pulse Width

500

ns

see note 2

NOTE

1 INTR

2 Pulse width of initial Reset pulse after power on must be at least 50 mSec Subsequent Reset pulses may be 500 ns

minimum The output Ports A B or C may glitch low during the reset pulse but all port pins will be held at a logic ‘‘one’’ level

after the reset pulse

20