28F004B5 datasheet(21/38 Pages) INTEL

21 / 38 page

SMART 5 BOOT BLOCK MEMORY FAMILY

ADVANCE INFORMATION

SR.7 = 1

YES

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read

Status Register

PP Range Error

Bus

Operation

Command

Comments

Standby

Check SR.3

1 = V

PP Low Detect

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command, in cases

where multiple bytes are programmed before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

Bus

Operation

Command

Comments

Write

Setup

Program

Data = Data to Program

Addr = Location to Program

Read

Data = 40H

Addr = Word/Byte to Program

Check SR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent word/byte program operations.

SR Full Status Check can be done after each word/byte

program operation, or after a sequence of word/byte programs.

Write FFH after the last program operation to reset device to

read array mode.

Standby

SR.3 =

SR.4 =

Word/Byte Program

Error

Word/Byte Program

Successful

Check SR.4

1 = Word Byte Program Error

Program

Status Register Data

Toggle CE# or OE#

to Update SRD.

0599-07

Figure 8. Automated Word/Byte Program Flowchart

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