ICS2595 datasheet(4/12 Pages) ICST

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ICS2595

LATCHED FS inputs, not the FS inputs themselves, that

are interpreted by the internal logic. Interface logic resides

between the FS input pins and the programming/frequency

select logic. The appropriate "data write" procedure must

be observed. See the section "Digital Interface" in this

supplement for more information.

These rules must be followed:

•

Calculate Tmax and Tmin in seconds (where R is the

modulus of the reference divider and Fref is the

reference frequency in Hz) by the following formulas:

•

A programming sequence consists of 42 successive

data writes to the device as shown in table 1: no delay

greater than Tmax or less than Tmin may occur between

any two successive writes.

•

A readback sequence consists of 64 successive data

writes to the device as shown in table 2: no delay

greater than Tmax or less than Tmin may occur between

any two successive writes.

•

Programming or readback sequences must be preceded

by a "quiet" period of at least 2* Tmax with no data

writes to the device unless it was immediately preceded

by another legal programming (or readback) sequence

(nothing else in between)

•

To change the active VCLK frequency selection, simply

write that data to the device; the last data written to the

part will always become VCLK frequency select after

a delay of approximately 2* Tmax. The internal shift

The FS0 & FS1 inputs are not used for programming, so it

is possible to use a two-pin interface for programming and

frequency selection (any bank of four VCLK addresses).

The reference frequency source must be operational for

proper execution of the programming sequence. If the on-

chip crystal oscillator is, allow at least 4* Tmax after the

device has valid power before attempting to program it.

Data Description

Location Bits (l0-L4)

The first five bits after the start bit control the frequency

location to be re-programmed according to this table. The

rightmost bit (the LSB) of the five shown in each

selection of the table is the first one sent.

)

(

Table 3 - Location Bit Programming

Feedback Set Bits (N0-N7)

These bits control the feedback divider setting for the

location specified. The modulus of the feedback divider

will be equal to the value of these bits + 257. The least

significant bit (N0) is sent first.

Post-Divider Set Bits (D0-D1)

These bits control the post-divider setting for the location

specified according to this table. The least significant bit

(D0) is sent first.

Table 4 - Post-Divider Programming

)

(

Tmin =

6* R

Fref

Tmax =

4096* R

Fref

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