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ICS1574B Folha de dados(PDF) 7 Page - Integrated Circuit Systems

Nome de Peças ICS1574B
Descrição Electrónicos  User Programmable Laser Engine Pixel Clock Generator
PDF  12 Pages
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Fabricante Electrônico  ICST [Integrated Circuit Systems]
Página de início  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1574B Folha de dados(HTML) 7 Page - Integrated Circuit Systems

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ICS1574B
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Register Mapping — ICS1574B
NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
BIT REF.
DESCRIPTION
1 – 4
PCLK[0]..PCLK[3]
Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
(X = Don't Care)
5, 6
Reserved
Must be set to 0.
7
Reserved
Must be set to 1.
8
SELXTAL
Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
9
Reserved
Must be set to 0.
10
Reserved
Must be set to 1.
11, 12
Reserved
Must be set to 0.
13 – 14
S[0]..S[1]
PLL post-scaler / test mode select bits.



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