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STAC9704 Folha de dados(PDF) 34 Page - Hynix Semiconductor

Nome de Peças STAC9704
Descrição Electrónicos  Multimedia Audio Codec for AC97
PDF  49 Pages
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Fabricante Electrônico  HYNIX [Hynix Semiconductor]
Página de início  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

STAC9704 Folha de dados(HTML) 34 Page - Hynix Semiconductor

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SigmaTel, Inc.
STAC9704/7
34
10/02/98
7. AC TIMING CHARACTERISTICS
(Tambient = 25
° C, AVdd = DVdd = 5.0V or 3.3V
± 5%, AVss=DVss+0V; 50pF external load)
7.1 Cold Reset
Figure 14: Cold Reset
RESET#
BIT_CLK
Tres_low
Trst2clk
Table 19 : Cold Reset
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RESET# active low pulse width
Tres_low
1.0
-
-
us
RESET# inactive to BIT_CLK startup delay
Trst2clk
162.8
-
-
ns
# denotes active low.
7.2 Warm Reset
As per the STAC9704 errata, the BIT_CLK is triggered on the rising edge of the SYNC pulse rather than the falling edge
of the SYNC pulse as specified in the AC97 specification. This issue is not known to have caused any customer problems.
Figure 15: Warm Reset
SYNC
BIT_CLK
Tsync_2clk
Tsync_high



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