10

TSC695F

4118J–AERO–08/04

It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register

are cleared automatically when the interrupt is acknowledged.

By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active

high and to define the external interrupts to either be edge or level sensitive.

Data access exception

(Error on data load)

10

09h

Idem “instruction access”

System register access violation

Tag overflow

11

0Ah

TADDccTV and TSUBccTV instructions

Trap instructions

12

80h to FFh

Trap on integer condition codes (Ticc)

Table 4. Synchronous Traps (Continued)

Trap

Priority

Trap Type (tt) Comments

Table 5. Interrupts or Asynchronous Traps

Trap

Priority

Watchdog time-out

13

1Fh

Internal or external (EWDINT pin)

External INT 4

14

1Eh

EXTINTAK on only one of EXTINT[4:0]

Real time clock timer

15

1Dh

–

General purpose timer

16

1Ch

–

External INT 3

17

1Bh

EXTINTAK on only one of EXTINT[4:0]

External INT 2

18

1Ah

EXTINTAK on only one of EXTINT[4:0]

DMA time-out

19

19h

–

DMA access error

20

18h

–

UART Error

21

17h

–

Correctable error in memory

22

16h

Data read OK but source not updated

UART B

Data ready

Transmitter ready

23

15h

–

UART A

Data ready

Transmitter ready

24

14h

–

External INT 1

25

13h

EXTINTAK on only one of EXTINT[4:0]

External INT 0

26

12h

EXTINTAK on only one of EXTINT[4:0]

Masked hardware errors

27

11h

Logical OR of:

IU hardware error masked

IU error mode masked

System hardware error masked