HT48CA0 datasheet(13/36 Pages) HOLTEK

13 / 36 page

To guarantee that the system oscillator has

started and stabilized, the SST (System Start-

up Timer) provides an extra-delay of 1024 sys-

tem clock pulses when the system powers up or

when the system awakes from a HALT state.

When a system power up occurs, an SST delay

is added during the reset period. But when the

reset comes from the RES pin, the SST delay is

disabled. Any wake-up from HALT will enable

the SST delay.

The functional unit chip reset status is shown

below.

000H

WDT Prescaler

Clear

Input/output Ports

Input mode

Points to the top of the

stack

Carrier Output

Low level

Reset configuration

Reset circuit

The chip reset status of the registers is summarized in the following table:

Reset

(power on)

WDT time-out

(normal

operation)

RES reset

(normal

operation)

RES reset

(HALT)

(Program Counter)

000H

-xxx xxxx

-uuu uuuu

ACC

xxxx xxxx

uuuu uuuu

TBLP

xxxx xxxx

uuuu uuuu

TBLH

--xx xxxx

--uu uuuu

STATUS

--00 xxxx

--1u uuuu

--uu uuuu

--01 uuuu

1111 1111

---- ---1

Notes: “u” means “unchanged”

“x” means “unknown”

Reset timing chart

HT48CA0

23rd July ’98

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