ADC102S021_14 datasheet(6/26 Pages) TI1

6 / 26 page

Track

Hold

Power Up

Track

Hold

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DIN

DOUT

Power Up

SCLK

Power Down

Control register

DB9

DB8

DB9

DB8

ADC102S021

SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013

www.ti.com

ADC102S021 Timing Specifications (continued)

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50

ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Parameter

Test Conditions

Typ

Limits(1)

Units

VA = +3.0V

tEN

Delay from CS Until DOUT active

ns (max)

VA = +5.0V

VA = +3.0V

+16.5

tACC

Data Access Time after SCLK Falling Edge

ns (max)

VA = +5.0V

+15

tSU

Data Setup Time Prior to SCLK Rising Edge

ns (min)

Data Valid SCLK Hold Time

ns (min)

tCH

SCLK High Pulse Width

0.5 x tSCLK 0.3 x tSCLK

ns (min)

tCL

SCLK Low Pulse Width

0.5 x tSCLK 0.3 x tSCLK

ns (min)

VA = +3.0V

1.7

Output Falling

VA = +5.0V

1.2

tDIS

CS Rising Edge to DOUT High-Impedance

ns (max)

VA = +3.0V

1.0

Output Rising

VA = +5.0V

1.0

Timing Diagrams

Figure 3. ADC102S021 Operational Timing Diagram

Figure 4. Timing Test Circuit

Submit Documentation Feedback

Product Folder Links: ADC102S021

ADC102S021 Folha de dados(PDF) 6 Page - Texas Instruments

ADC102S021 Folha de dados(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Folha de dados Download

Ligação URL