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ADDR10 Folha de dados(PDF) 65 Page - List of Unclassifed Manufacturers |
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ADDR10 Folha de dados(HTML) 65 Page - List of Unclassifed Manufacturers |
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65 / 68 page ![]() Serial in te rn al/external tim i ng ww w.d i gi .c om 61 Serial internal/external timing Operating conditions: Note: SPI timing diagrams are in Chapter 10, "Serial Controller Module." See Figure 25, "SPI master mode 0 and 1 two-byte transfer," on page 219 and Figure 26, "SPI slave mode 0 and 1 two-byte transfer," on page 222. Only SPI modes 0 and 1 are supported. Serial internal timing characteristics Serial external timing characteristics Temperature: -15.00 (min) 110.00 (max) Voltage: 1.60 (min) 1.40 (max) Output load: 25.0pf Input drive: CMOS buffer Num Description Min Max Unit 76 SCLK to ENABLE high 1 TSCLK 77 SCLK to TXD (PORTA7/C7) 1 TSYS*ns 78 RXD (PORTA3/C3) setup to SCLK 1 ns 79 RXD hold to SCLK 1 ns * The TSYS parameter represents one period of the internal system clock. Num Description Min Max Unit 80 SCLK frequency 10 MHz SCLK duty cycle 45 55 % 81 SCLK to ENABLE 1 TSCLK 82 SCLK to TXD (PORTA7/C7) 2TSYS*ns 83 RXD (PORTA3/C3) setup to SCLK 2 ns 84 RXD hold to SCLK 1.5 ns * The TSYS parameter represents one period of the internal system clock. |
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