CS43L41 datasheet(30/36 Pages) CIRRUS

30 / 36 page

CS43L41

DS473PP1

LRCK

SCLK

Left Channel

Right Channel

SDATA

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

I2S, Up to 24-Bit data and INT SCLK = 64 Fs if

MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data

and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

I2S, up to 24-Bit DataData Valid on Rising Edge of

SCLK

Figure 20. CS43L41 Format 0 (I2S)

LRCK

SCLK

Left Channel

Right Channel

SDATA

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

I2S, 16-Bit data and INT SCLK = 32 Fs if

MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data

and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

I2S, up to 24-Bit DataData Valid on Rising Edge of

SCLK

Figure 21. CS43L41 Format 1 (I2S)

LRCK

SCLK

Left Channel

Right Channel

SDATA

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

Left Justified, up to 24-Bit DataINT SCLK = 64 Fs if

MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if

MCLK/LRCK = 384 or 192

Left Justified, up to 24-Bit DataData Valid on Rising

Edge of SCLK

Figure 22. CS43L41 Format 2

CS43L41 Folha de dados(PDF) 30 Page - Cirrus Logic

CS43L41 Folha de dados(HTML) 30 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Folha de dados Download

Ligação URL