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THS7530PWPR Folha de dados(PDF) 2 Page - National Semiconductor (TI) |
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THS7530PWPR Folha de dados(HTML) 2 Page - National Semiconductor (TI) |
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2 / 24 page ![]() THS7530 SLOS405C – DECEMBER 2002 – REVISED FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION(1) PART NUMBER PACKAGE TYPE PACKAGE MARKING TRANSPORT MEDIA, QUANTITY THS7530PWP Rails, 90 TSSOP-14-PP THS7530 THS7530PWPR Tape and Reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. THS7530 VS+ – VS– Supply voltage 5.5 V VI Input voltage ±VS IO Output current 65 mA VID Differential input voltage ±4 V Continuous power dissipation See Dissipation Rating Table Maximum junction temperature +150°C TJ Maximum junction temperature for long term stability(2) +125°C Tstg Storage temperature range –65°C to +150°C HBM 3000 V ESD CDM 1500 V MM 200 V (1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. PACKAGE THERMAL DATA qJA qJC TA = 25°C PACKAGE PCB (°C/W) (°C/W)(1) POWER RATING(2) PWP (14-pin)(3) See Layout Considerations in the Application section of this data sheet. 37.5 2.07 3 W (1) This data was taken using the JEDEC High-K test printed circuit board (PCB). (2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in x 3 in PCB. (3) The THS7530 incorporates a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD thermally enhanced package. RECOMMENDED OPERATING CONDITIONS TEST CONDITIONS MIN TYP MAX UNIT [VS- to VS+] Supply voltage 4.5 5 5.5 V TA Operating free-air temperature –40 +85 °C Input common mode voltage [VS- to VS+] = 5 V 2.5 V Output common mode voltage [VS- to VS+] = 5 V 2.5 V 2 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): THS7530 |
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