ADP3208A datasheet(21/38 Pages) AD

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ADP3208A

Rev. 2 | Page 21 of 38 | www.onsemi.com

limit alert is released and the control of the internal COMP

voltage is transferred from the voltage error amplifier to the

current limit amplifier to maintain an average output current

determined by the set current limit level.

When the output voltage is less than 200 mV during start-up, a

secondary current limit is activated. This is necessary because

the voltage swing on the CSCOMP cannot extend below ground.

The secondary current limit circuit clamps the internal COMP

voltage at around 1.6 V, resulting in duty cycle limited operation.

There is also an inherent per phase current limit that protects

individual phases in case any of the phases stop functioning due

to a faulty component. This limit is based on the maximum

normal mode COMP voltage.

If the output current exceeds the current limit threshold or

the output voltage is outside the PWRGD range, the SS pin is

discharged by an internal sink current of 2 μA. A comparator

monitors the SS pin voltage and shuts off the controller when

the voltage drops to less than about 1.65 V. Because the voltage

ramp (2.9 V − 1.65 V = 1.25 V) and the discharge current (2 μA)

are internally fixed, the current limit latch-off delay time is

determined by the external SS pin capacitor selection.

Figure 28 shows how the ADP3208 reacts to a current overload.

1ms/DIV

CURRENT LIMIT

APPLIED

LATCHED

OFF

SWITCH NODE 10V/DIV

SS PIN 2V/DIV

PWRGD 2V/DIV

OUTPUT VOLTAGE 1V/DIV

Figure 28. Current Overload

The controller cycles the phases during the latch-off delay time.

If the current overload is removed and the PWRGD is recovered

before the 1.65 V threshold is reached, the controller resumes

normal operation and the SS pin voltage recovers to a 2.9 V

clamp level.

The latch off can be reset by either removing and reapplying

VCC or by briefly cycling the EN pin low and high. To disable

the current limit latch-off function, an external pull-up resistor

can be tied from the SS pin to the VCC rail. The pull-up current

must override the 2 μA sink current of the SS pin to prevent the

SS capacitor from discharging to a voltage level that is less than

the 1.65 V latch-off threshold.

CHANGING VID ON THE FLY

The ADP3208 is designed to track dynamically changing VID

code. As a consequence, the CPU VCC voltage can change

without the need to reset the controller or the CPU. This

concept is commonly referred to as VID on-the-fly (VID OTF)

transient. A VID OTF can occur with either light or heavy load

conditions. The processor alerts the controller that a VID

change is occurring by changing the VID inputs in LSB

incremental steps from the start code to the finish code. The

change can be either upwards or downwards steps.

When a VID input changes, the ADP3208 detects the change

but ignores new code for a minimum of 400 ns. This delay is

required to prevent the device from reacting to digital signal

skew while the 7-bit VID input code is in transition. Additionally,

the VID change triggers a PWRGD masking timer to prevent

a PWRGD failure. Each VID change resets and retriggers the

internal PWRGD masking timer.

As listed in Table 6, during a VID transient, the ADP3208 forces

PWM mode regardless of the state of the system input signals.

For example, this means that if the chip is configured as a dual-

phase controller but is running in single-phase mode due to a

light load condition, a current overload event causes the chip to

switch to dual-phase mode to share the excessive load until the

delayed current limit latch-off cycle terminates.

In user-set single-phase mode, the ADP3208 usually runs in

RPM mode. When a VID transition occurs, however, the

ADP3208 switches to dual-phase PWM mode.

Light Load RPM DCM Operation

In single-phase normal mode, DPRSLP is pulled low and the

APD3208 operates in continuous conduction mode (CCM)

over the entire load range. The upper and lower MOSFETs are

always running synchronously and in complementary phase.

See Figure 29 for the typical waveforms of the ADP3208

running in CCM with a 7 A load current.

400ns/DIV

OUTPUT VOLTAGE 20mV/DIV

INDUCTOR CURRENT 5A/DIV

SWITCH NODE 5V/DIV

LOW-SIDE GATE DRIVE 5V/DIV

Figure 29. Single-Phase Waveforms in CCM

If DPRSLP is pulled high, the ADP3208 operates in RPM mode.

If the load condition is light, the chip enters discontinuous con-

duction mode (DCM). Figure 30 shows a typical single-phase

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