74LVC00A

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 7 — 25 April 2012

7 of 14

NXP Semiconductors

74LVC00A

Quad 2-input NAND gate

12. Package outline

Fig 8.

Package outline SOT108-1 (SO14)

UNIT

A

max.

(1)

QZ

y

w

v

θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8

0

o

o

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

X

θ

A

D

Q

detail X

E

Z

e

c

L

(A )

3

A

7

8

1

14

y

076E06

MS-012

pin 1 index

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.35

0.34

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.024

0.028

0.012

0.01

0.25

0.01

0.004

0.039

0.016

99-12-27

03-02-19

0

2.5

5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1