AS3953_07 datasheet(10/42 Pages) AMSCO

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AS3953

Datasheet - D e t a il e d D es c r i pt io n

Clock Extractor: The clock extractor extracts a digital clock signal from the PCD carrier field frequency which is used as clock signal by logic

blocks.

HF_PON: Observes rectified regulated voltage VREC. When the supply voltage is sufficiently high it enables operation of the PICC AFE and

the digital tag logic. A buffer capacitor and HF_PON hysteresis guarantees that there is no reset during reader (PCD) modulation.

Internal Regulator: Provides regulated voltage VP_INT to the PICC AFE and in most cases also to EEPROM and logic blocks. Typical

regulated voltage VP_INT is 2.0V. A buffer capacitor is also integrated.

External Regulator: Provides regulated voltage on external pin VP_REG where it can be used to supply some external circuitry. The

regulated voltage and output resistance can be adjusted using EEPROM settings (see Table 6). Appropriate external buffer capacitor is needed

in case VP_REG is used in the application. The current to be provided depends on reader field strength, antenna size and Q factor, but it is

limited to maximum 5mA.

Bias: Provides bias currents and reference voltages to PICC AFE analog blocks.

Figure 4. PICC AFE Block Diagram

PON

Rectifier

Modulator

Switch

Limiter

Demodulator

Clock

Extractor

LC1

LC2

ISO 14443 A

LOGIC

External

Regulator

BIAS

VP_REG

Internal

Regulator

VP_INT

VREC

AS3953

AS3953 Folha de dados(PDF) 10 Page - ams AG