PIC16C72 datasheet(67/337 Pages) MICROCHIP

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DS30234D-page 67

PIC16C6X

7.2

Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 7-5).

Therefore, it is necessary for T0CKI to be high for at

least 2Tosc (and a small RC delay of 20 ns) and low for

at least 2Tosc (and a small RC delay of 20 ns). Refer to

the electrical speciﬁcation of the desired device.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4Tosc (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 41 and 42 in the electrical speciﬁcation of the

desired device.

7.2.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 7-5 shows the delay

from the external clock edge to the timer incrementing.

FIGURE 7-5:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q2 Q3 Q4

Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output (2)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input =

±4Tosc max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

Small pulse

misses sampling

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