TPS72201, TPS72215

TPS72216, TPS72218

SLVS390B – DECEMBER 2001 – REVISED MAY 2002

www.ti.com

2

Thesedevices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

TJ

VOLTAGE

PACKAGE

PART NUMBER

SYMBOL

Adjustable

TPS72201DBVT(1)

TPS72201DBVR(2)

PELI

40

°Cto125°C

1.5 V

SOT-23

TPS72215DBVT(1)

TPS72215DBVR(2)

PENI

–40

°C to 125°C

1.6 V

SOT 23

(DBV)

TPS72216DBVT(1)

TPS72216DBVR(2)

PHGI

1.8 V

TPS72218DBVT(1)

TPS72218DBVR(2)

PEMI

(1) The DBVT indicates tape and reel of 250 parts.

(2) The DBVR indicates tape and reel of 3000 parts.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

TPS72201,TPS72215

TPS72216,TPS72218

Input voltage range (1)

– 0.3 V to 7 V

Voltage range at EN

–0.3 V to 7 V

Voltage on OUT, FB, NC

–0.3 V to VI + 0.3 V

Peak output current

Internallylimited

ESD rating, HBM

3 kV

Continuous total power dissipation

See Dissipation Rating Table

Operating virtual junction temperature range, TJ

– 40

°C to 150°C

Storage temperature range, Tstg

–65

°C to 150°C

(1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

PACKAGE DISSIPATION RATING

BOARD

PACKAGE

R

θJC

R

θJA

DERATING FACTOR

ABOVE TA = 25°C

TA ≤ 25°C

POWER RATING

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

Low K(1)

DBV

65.8

°C/W

259

°C/W

3.9 mW/

°C

386 mW

212 mW

154 mW

High K(2)

DBV

65.8

°C/W

180

°C/W

5.6 mW/

°C

555 mW

305 mW

222 mW

(1) TheJEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2 ounce copper traces on top of theboard.

(2) The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground

planes and 2 ounce copper traces on top and bottom of the board.