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TLC32046MFKB Folha de dados(PDF) 41 Page - Texas Instruments

Nome de Peças TLC32046MFKB
Descrição Electrónicos  Wide-Band Analog Interface Circuit
PDF  56 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
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TLC32046MFKB Folha de dados(HTML) 41 Page - Texas Instruments

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SHIFT
CLK
FSR,
FSX
EODR,
EODX
DR
DX
td (CH-FL)
2 V
t f (SCLK)
t r (SCLK)
2 V
td (CH-FH)
2 V
td (CH-FL)
2 V
2 V
td (CH-FH)
tc (SCLK)
2 V
8 V
2 V
2 V
td (CH-DR)
8 V
D15
D14
D13
D9
D8
D7
D6
D2
D1
D0
D12
D11
D8
Don’t Care
D13
D9
D15
D14
D0
D2
D1
tsu (DX)
th (DX)
td (CH-EL)
8 V
2 V
The time between falling edges of FSR is the A/D conversion period, and the time between fallling edges of FSX is the D/A conversion period.
In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.
†
Figure 4–4. Byte-Mode Timing
‡
td (CH-EH)



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