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STM32F217VG Folha de dados(PDF) 87 Page - STMicroelectronics |
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STM32F217VG Folha de dados(HTML) 87 Page - STMicroelectronics |
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87 / 173 page  STM32F21xxx Electrical characteristics Doc ID 17050 Rev 8 87/173 Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N=432, R=5 on 1000 samples -90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples -400 - ps IDD(PLLI2S) (4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S) (4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Table 32. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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