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STM32F205RB Folha de dados(PDF) 27 Page - STMicroelectronics |
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STM32F205RB Folha de dados(HTML) 27 Page - STMicroelectronics |
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27 / 178 page ![]() DocID15818 Rev 11 27/178 STM32F20xxx Functional overview 177 Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD time 1.08 V PDR=1.8 V VCAP_1/VCAP_2 1.2 V time PA0 tied to NRST NRST VDD time 1.08 V PDR=1.8 V VCAP_1/VCAP_2 1.2 V time PA0 asserted externally NRST |
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