LP61L256C datasheet(8/11 Pages) AMICC

Nome de Peças	LP61L256C

Descrição Electrónicos	32K X 8 BIT HIGH SPEED CMOS SRAM

PDF	11 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AMICC [AMIC Technology]

Página de início	http://www.amictechnology.com

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8 / 11 page

LP61L256C Series

PRELIMINARY

(November, 2001, Version 0.0)

AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 1

(6)

(Write Enable Controlled)

tWC

Address

DIN

tOW7

tDH

tDW

tWHZ7

tWP2

tAS1

(4)

tCW5

tAW

tWR3

DOUT

Write Cycle 2

(Chip Enable Controlled)

tWC

Address

DIN

tDW

tWHZ7

tAW

tWR3

DOUT

tDH

(4)

tWP2

tCW5

tAS1

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE and a low WE .

3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle

4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs

remain in a high impedance state.

5. tCW is measured from the later of CE going low to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured

±200mV from steady state. This parameter is sampled and not 100% tested.

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