PSD813F2 datasheet(77/128 Pages) STMICROELECTRONICS

Nome de Peças	PSD813F2

Descrição Electrónicos	Flash in-system programmable (ISP) peripherals

PDF	128 Pages

Scroll/Zoom	100%

Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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77 / 128 page

PSD8XXFX

I/O ports

Doc ID 7833 Rev 7

77/128

Port D pins can be configured in PSDsoft Express as input pins for other dedicated

functions:

●

Address Strobe (ALE/AS, PD0)

●

CLKIN (PD1) as input to the macrocells flip-flops and APD counter

●

PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,

SRAM and CSIOP.

Figure 29.

Port D structure

16.23

External Chip Select

The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins

that can be used to select external devices. Each External Chip Select (ECS0-ECS2)

consists of one product term that can be configured active high or low. The output enable of

the pin is controlled by either the output enable product term or the Direction register (see

Figure 30).

DATA OUT

REG.

ECS[ 2: 0]

READ MUX

CPLD - INPUT

DIR REG.

DATA IN

ENABLE PRODUCT

TERM (.OE)

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

AI02889

Obsolete

Product(s)

- Obsolete

Product(s)

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