AM7968-125JC datasheet(85/127 Pages) AMD

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AMD

TAXIchip Integrated Circuits Technical Manual

The Data Out Lines

When a Receiver sees the Sync symbol it sends the data byte it just received from its

Input Latch to its Decoder Latch, and then the receiver lowers its IGM. One more clock

cycle is required for the data to go to the Output Latch. At this point DSTRB is raised. In

this way all data bytes are output simultaneously from all receivers, two clock cycles

after the first Sync (or two clock cycles after a LOW CNB). The DSTRBs of all the

receivers rise simultaneously as well.

The VLTN (Violation) Pin

In Cascade mode the VLTN pin acts exactly like a Data Out line. The timings are exactly

the same. Violations do not change the output of the IGM pin. i.e., a Receiver that gets a

VLTN will still raise it’s IGM signal as if it received a valid data byte.

7.3 Auto-Repeat Configuration

7.3.1 Receiver Connections in Auto-Repeat Configuration

In Auto-repeat Configuration the IGM of the last Receiver on the line is inverted and tied

to the CNB of the Primary Receiver. This connection eliminates the need to send a Sync

between each Data Word.

In a 3-Receiver cascade system, IGM3 is inverted and tied to CNB1. When the IGM of

the last Receiver goes high, CNB1 goes LOW.

CNB1 going LOW ripples through the chain pulling each IGM LOW (t46 ns) until finally

the last IGM goes LOW again, pulling CNB1 HIGH resetting RX1 to receive new data.

In Figures 7-6 and 7-7, as each Receiver decodes its data byte, it raises its IGM and

thus the next Receiver’s CNB.

Figure 7-6

TAXI Receiver—Cascaded in Auto-Repeat

SERIN+

SERIN–

CNB

IGM

DSTRB

CSTRB

CNB

IGM

DSTRB

CSTRB

CNB

IGM

DSTRB

CSTRB

CNB

IGM

DSTRB

CSTRB

12330E-28

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