AD7870LP datasheet(20/28 Pages) AD

20 / 28 page

AD7870/AD7875/AD7876

Rev. C | Page 20 of 2

This is a two-byte read instruction. During the first read

operation BUSY, in conjunction with CS, forces the micro-

processor to WAIT for the ADC conversion. At the end of

conversion the ADC low byte (DB7 – DB0) is loaded into

D15 – D8 of the D0 register and the ADC high byte (DB15 –

DB7) is loaded into Bits D7 – D0 of the D0 register.

The following rotate instruction to the D0 register swaps the

high and low bytes to the correct format.

R0L = 8, D0.

Note that while executing the two-byte read instruction above,

WAIT states are inserted during the first read operation only

and not for the second.

A15

CONVST

HBEN

12/8/CLK

BUSY/INT

DB7

DB0

ADDRESS BUS

DATA BUS

ADDR

DECODE

DTACK

STRB

D15

R/W

1ADDITIONAL PINS OMITTED FOR CLARITY.

2RESISTOR AND CAPACITOR REQUIRED TO GUARANTEE

t15.

AD7870/

AD7875/

AD78761

MC68008

Figure 25. MC68008 Byte Interface

SERIAL INTERFACING

Figure 26, Figure 27, Figure 28, and Figure 29 show the

AD7870/AD7875/AD7876 configured for serial interfacing. In

all four interfaces, the ADC is configured for Mode 1 operation.

The interfaces show a timer driving the CONVST input, but

this could be generated from a decoded address if required. The

SCLK, SDAT and SSTRB are open-drain outputs. If these are

required to drive capacitive loads in excess 35 pF, buffering is

recommended.

DSP56000 Serial Interface

Figure 26 shows a serial interface between the AD7870/AD7875/

AD7876, and the DSP56000. The interface arrangement is

two-wire with the ADC configured for noncontinuous clock

operation (12/8/CLK = 0 V). The DSP56000 is configured

for normal mode asynchronous operation with gated clock.

It is also set up for a 16-bit word with SCK and SC1 as inputs

and the FSL control bit set to a 0. In this configuration, the

DSP56000 assumes valid data on the first falling edge of SCK.

Since the ADC provides valid data on this first edge, there is

no need for a strobe or framing pulse for the data. SCLK and

SDATA are gated off when the ADC is not performing a

conversion. During conversion, data is valid on the SDATA

output of the ADC and is clocked into the receive data shift

16 bits of data, it generates an internal interrupt on the

DSP56000 to read the data from the register.

CONVST

12/8/CLK

SCLK

2kΩ

4.7kΩ

SDATA

SCK

SRD

DSP56000

TIMER

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD7870/

AD7875/

AD78761

Figure 26. DSP56000 Serial Interface

The DSP56000 and AD7870/AD7875/AD7876 can also be

configured for continuous clock operation (12/8/CLK = −5 V).

In this case, a strobe pulse is required by the DSP56000 to

indicate when data is valid. The SSTRB output of the ADC

is inverted and applied to the SC1 input of the DSP56000 to

provide this strobe pulse. All other conditions and connections

are the same as for gated clock operation.

NEC7720/77230 Serial Interface

A serial interface between the AD7870/AD7875/AD7876 and

the NEC7720 is shown in Figure 27. In the interface shown, the

ADC is configured for continuous clock operation. This can be

changed to a noncontinuous clock by simply tying the 12/8/CLK

input of the ADC to 0 V with all other connections remaining

the same. The NEC7720 expects valid data on the rising edge of

its SCK input and therefore an inverter is required on the SCLK

output of the ADC. The NEC7720 is configured for a 16-bit

data word. Once the 16 bits of data have been received by the SI

read the contents of the SI register.

The NEC77230 interface is similar to that just outlined for the

NEC7720. However, the clock input of the NEC77230 is SICLK.

Additionally, no inverter is required between the ADC SCLK

output and this SICLK input since the NEC77230 assumes data

is valid on the falling edge of SICLK.

CONVST

12/8/CLK

2kΩ

+5V

–5V

4.7kΩ

SCLK

SIEN

SCLK

SSTRB

SDATA

µPD7720

TIMER

1ADDITIONAL PINS OMITTED FOR CLARITY.

AD7870/

AD7875/

AD78761

Figure 27. NEC7720 Serial Interface

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