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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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PIC18F2680ISOSQTP Folha de dados(PDF) 260 Page - Microchip Technology |
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PIC18F2680ISOSQTP Folha de dados(HTML) 260 Page - Microchip Technology |
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260 / 482 page  PIC18F2585/2680/4585/4680 DS39625C-page 258 Preliminary © 2007 Microchip Technology Inc. 20.1 Comparator Configuration There are eight modes of operation for the compara- tors, shown in Figure 20-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The TRISA register controls the data direction of the com- parator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 27.0 “Electrical Characteristics”. FIGURE 20-1: COMPARATOR I/O OPERATING MODES Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. C1 VIN- VIN+ Off Comparators Reset (POR Default Value) A A CM2:CM0 = 000 C2 VIN- VIN+ Off A A C1 VIN- VIN+ C1OUT Two Independent Comparators A A CM2:CM0 = 010 C2 VIN- VIN+ C2OUT A A C1 VIN- VIN+ C1OUT Two Common Reference Comparators A A CM2:CM0 = 100 C2 VIN- VIN+ C2OUT A D C2 VIN- VIN+ Off One Independent Comparator with Output D D CM2:CM0 = 001 C1 VIN- VIN+ C1OUT A A C1 VIN- VIN+ Off Comparators Off D D CM2:CM0 = 111 C2 VIN- VIN+ Off D D C1 VIN- VIN+ C1OUT Four Inputs Multiplexed to Two Comparators A A CM2:CM0 = 110 C2 VIN- VIN+ C2OUT A A From VREF Module CIS = 0 CIS = 1 CIS = 0 CIS = 1 C1 VIN- VIN+ C1OUT Two Common Reference Comparators with Outputs A A CM2:CM0 = 101 C2 VIN- VIN+ C2OUT A D A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch CVREF C1 VIN- VIN+ C1OUT Two Independent Comparators with Outputs A A CM2:CM0 = 011 C2 VIN- VIN+ C2OUT A A * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. (Read as ‘0’) (Read as ‘0’) (Read as ‘0’) (Read as ‘0’) (Read as ‘0’) RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RD1/PSP1/ RD0/PSP0/ RD3/PSP3/ RD2/PSP2/ C2IN- C2IN+ C1IN+ C1IN- RE1/WR/AN6/C1OUT* RE1/WR/AN6/C1OUT* RE2/CS/AN7/C2OUT* RD1/PSP1/C1IN- RD0/PSP0/C1IN+ RD3/PSP3/C2IN- RD2/PSP2/C2IN+ RE1/WR/AN6/C1OUT* RE2/CS/AN7/C2OUT* |
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