PCM3010

SLES055 – NOVEMBER 2002

22

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system clock (continued)

tSCKH

System Clock

0.8 V

2.0 V

tSCKL

1/128 fS or 1/192 fS

1/256 fS or 1/384 fS

1/512 fS or 1/768 fS

PARAMETER

MIN

MAX

UNIT

tSCKH

System clock pulse duration HIGH

8

ns

tSCKL

System clock pulse duration LOW

8

ns

Figure 44. System Clock Timing

power supply on, external reset, and power down

The PCM3010 has both an internal power-on reset circuit and an external reset circuit. The sequences for both

resets are explained as follows.

Figure 45 is the timing diagram for the internal power-on reset. Two power-on reset circuits are implemented

2.2 V, typically.

Internal reset is released 1024 SCKI clock cycles following the release from power-on reset, and the PCM3010

reset is not released and device operation remains in the power-down mode. After resynchronization, the DAC

performs the fade-in sequence and the ADC resumes normal operation following internal initialization.

Figure 46 is the external-reset timing diagram. External forced reset, driving the PDWN pin LOW, puts the

PCM3010 in the power-down mode, which is its lowest power-dissipation state.

When PDWN transitions from HIGH to LOW while synchronization is maintained between SCKI, BCK, and

At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3010 enters into

power-down mode. To enter into normal operation mode again, change PDWN to HIGH again. The reset

sequence shown in Figure 45 occurs.

Notes:

1.

normal operation.

2.

To switch PDWN during fade in or fade out causes an immediate change between fade in and fade out.

3.

To switch the control pins on the fly during normal operation can degrade analog performance. It is

recommended that changing control pins, changing clocks, stopping clocks, turning power supplies off, etc.,

be done in the power-down mode.