AT90USB646 datasheet(13/456 Pages) ATMEL

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7593L–AVR–09/12

AT90USB64/128

5.4

Status register

The status register contains information about the result of the most recently executed arithmetic

instruction. This information can be used for altering program flow in order to perform conditional

operations. Note that the status register is updated after all ALU operations, as specified in the

Instruction Set Reference. This will in many cases remove the need for using the dedicated com-

pare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

The AVR status register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction set summary” on page 423 for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction set summary” on page 423 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction set summary” on page 423 for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction set summary” on page 423 for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

set summary” on page 423 for detailed information.

Bit

76543210

SVN

SREG

Read/write

R/W

Initial value

00000000

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