HEF4094B

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Product data sheet

Rev. 11 — 29 August 2013

4 of 20

NXP Semiconductors

HEF4094B

8-stage shift-and-store register

6.

Functional description

[1]

At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = positive-going transition;  = negative-going transition;

Z = HIGH-impedance OFF-state; NC = no change;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

Table 3.

Function table[1]

Inputs

Parallel outputs

Serial outputs

CP

OE

STR

D

QP0

QPn

QS1

QS2



L

XXZ

Z

Q6S

NC



L

XXZ

Z

NC

Q7S



HL

X

NC

NC

Q6S

NC



HH

L

L

QPn

1Q6S

NC



H

HHH

QPn

1Q6S

NC



H

H

H

NC

NCNCQ7S

Fig 6.

Timing diagram

001aaf117

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

INTERNAL Q6S (FF 6)

OUTPUT QP6

SERIAL OUTPUT QS1

SERIAL OUTPUT QS2

Z-state

Z-state