TLC7528C, TLC7528E, TLC7528I

DUAL 8BIT MULTIPLYING

DIGITALTOANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

10

POST OFFICE BOX 655303

APPLICATION INFORMATION

WR

Address

Decode

Logic

Address Bus

Data Bus

D0 − D7

DB7

DB0

WR

CS

DACA/DACB

TLC7528

IORQ

CPU

Z80-A

A8 − A15

A

A + 1

NOTE A: A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

8

8

Figure 7. TLC7528 To Z-80A Interface

programmable window detector

The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC

feedback resistors is within the limits programmed into the data latches of these devices. Input signal range

latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the

output high.