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LP2995M Folha de dados(PDF) 9 Page - Texas Instruments |
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LP2995M Folha de dados(HTML) 9 Page - Texas Instruments |
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9 / 22 page ![]() 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) SOP Board JEDEC Board 150 160 140 170 180 100 110 120 130 80 90 LP2995 www.ti.com SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013 performance are critical, although their cost is typically higher than any other capacitor. Capacitor recommendations for different application circuits can be seen in the accompanying application notes with supporting evaluation boards. Thermal Dissipation Since the LP2995 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax − TAmax From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / θJA The θJA of the LP2995 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Figure 14 shows how the θJA varies with airflow for the two boards mentioned. Figure 14. θJA vs Airflow (SOIC-8) Layout is also extremely critical to maximize the output current with the WQFN package. By simply placing vias under the DAP the θJA can be lowered significantly. Figure 15 shows the WQFN thermal data when placed on a 4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has been increased to the maximum of 4 where a θJA of 50.41°C/W can be obtained. Via wall thickness for this calculation is 0.036 mm for 1oz. Copper. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LP2995 |
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