LTC1293BCN datasheet(20/28 Pages) LINER

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LTC1293/LTC1294/LTC1296

129346fs

APPLICATI

I FOR ATIO

Figure 11. RC Input Filtering

RFILTER

VIN –

CFILTER

LTC1293 F11

LTC1293/4/6

"+"

"–"

IIDC

within the minimum settling windows of 2.5

µs (“+” input)

and 1

µs(“–” input) that occurs at the maximum clock rate

of 1MHz. Figures 9 and 10 show examples of adequate

and poor op amp settling.

RC Input Filtering

It is possible to filter the inputs with an RC network as

shown in Figure 11. For large values of CF (e.g., 1µF) the

capacitive input switching currents are averaged into a net

DC current. A filter should be chosen with a small resistor

and large capacitor to prevent DC drops across the resis-

tor. The magnitude of the DC current is approximately IDC

= 100pF

× VIN/tCYC and is roughly proportional to VIN.

When running at the minimum cycle time of 21.5

µs, the

input current equals 23

µA at VIN= 5V. Here a filter resistor

of 5

Ω will cause 0.1LSB of full-scale error. If a larger filter

resistor must be used, errors can be reduced by increasing

the cycle time as shown in the typical performance char-

acteristic curve Maximum Filter Resistor vs Cycle Time.

Input Leakage Current

Input leakage currents also can create errors if the source

resistance gets too large. For example, the maximum input

leakage specification of 1

µA (at 125°C) flowing through a

source resistance of 1k

Ω will cause a voltage drop of 1mV

or 0.8LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see typical

performance characteristic curve Input Channel Leakage

Current vs Temperature).

SAMPLE AND HOLD

Single-Ended Input

The LTC1293/4/6 provides a built-in sample and hold

(S&H) function for all signals acquired in the single-ended

mode (COM pin grounded). The sample and hold allows

the LTC1293/4/6 to convert rapidly varying signals (see

typical performance characteristic curve of S&H Acquisi-

tion Time vs Source Resistance). The input voltage is

sampled during the tSMPL time as shown in Figure 8. The

sampling interval begins as the bit preceding the MSBF bit

is shifted in and continues until the falling edge of the PS

bit is received. On this falling edge the S&H goes into the

hold mode and the conversion begins.

Differential Input

With a differential input the A/D no longer converts a

single voltage but converts the difference between two

voltages. The voltage on the selected “+” input is sampled

and held and can be rapidly time varying. The voltage on

the “–” pin must remain constant and be free of noise and

ripple throughout the conversion time. Otherwise the

differencing operation will not be done accurately. The

conversion time is 12 CLK cycles. Therefore a change in

the –IN input voltage during this interval can cause con-

version errors. For a sinusoidal voltage on the –IN input

this error would be:

Where f(–) is the frequency of the “–” input voltage, VPEAK

is its peak amplitude and fCLK is the frequency of the CLK.

ERROR MAX

PEAK

CLK

()

(–)

= π

()⎛

⎝⎜

⎞

⎠⎟

HORIZONTAL: 20

µs/DIV

HORIZONTAL: 500ns/DIV

Figure 9. Adequate Settling of Op Amp Driving Analog Input

Figure 10. Poor Op Amp Settling Can Cause A/D Errors

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