AD9709

Rev. B | Page 12 of 32

THEORY OF OPERATION

5V

CLK1/IQCLK CLK2/IQRESET

AVDD

FSADJ1

REFIO

FSADJ2

1.2V REF

CHANNEL 1 LATCH

CHANNEL 2 LATCH

MODE

DVDD1/

DVDD2

MULTIPLEXING LOGIC

5V

GAINCTRL

DCOM1/

DCOM2

SLEEP

ACOM

DVDD1/DVDD2

DCOM1/DCOM2

AD9709

2k

Ω

0.1µF

2k

Ω

CLK

DIVIDER

DAC1

LATCH

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

WRT1/

IQWRT

RETIMED CLOCK OUTPUT*

LECROY 9210

PULSE

GENERATOR

50

Ω

DIGITAL

DATA

TEKTRONIX

AWG2021

WITH OPTION 4

WRT2/

IQSEL

*AWG2021 CLOCK RETIMED SUCH THAT

DIGITAL DATA TRANSITIONS ON FALLING

EDGE OF 50% DUTY CYCLE CLOCK.

PORT 1

PORT 2

DAC2

LATCH

LSB

SWITCH

SEGMENTED

SWITCHES FOR

DAC2

SEGMENTED

SWITCHES FOR

DAC1

LSB

SWITCH

TO HP3589A

OR EQUIVALENT

SPECTRUM/

NETWORK

ANALYZER

Mini-Circuits

T1-1T

50

Ω

50

Ω

Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2

0.1µF

5V

CLK1/IQCLK

CLK2/IQRESET

AVDD

FSADJ1

REFIO

FSADJ2

1.2V REF

CHANNEL 1 LATCH

CHANNEL 2 LATCH

MODE

DVDD1/

DVDD2

MULTIPLEXING LOGIC

5V

GAINCTRL

DCOM1/

DCOM2

SLEEP

DIGITAL DATA INPUTS

AD9709

2k

Ω

2k

Ω

WRT1/

IQWRT

PORT 1

PORT 2

WRT2/

IQSEL

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

CLK

DIVIDER

DAC1

LATCH

DAC2

LATCH

SEGMENTED

SWITCHES FOR

DAC1

LSB

SWITCH

SEGMENTED

SWITCHES FOR

DAC2

LSB

SWITCH

50

Ω

50

Ω

50

Ω

50

Ω

ACOM

Figure 22. Simplified Block Diagram

FUNCTIONAL DESCRIPTION

Figure 22 shows a simplified block diagram of the AD9709. The

AD9709 consists of two DACs, each one with its own independent

digital control logic and full-scale output current control. Each

DAC contains a PMOS current source array capable of providing

The array is divided into 31 equal currents that make up the five

most significant bits (MSBs). The next four bits, or middle bits,

MSB current source. The remaining LSB is a binary weighted

fraction of the middle bit current sources. Implementing the

middle and lower bits with current sources instead of an R-2R

ladder enhances the dynamic performance for multitone or low

amplitude signals and helps maintain the high output impedance

of each DAC (that is, >100 kΩ).

All of these current sources are switched to one of the two

current switches. The switches are based on a new architecture

that drastically improves distortion performance. This new

switch architecture reduces various timing errors and provides

matching of complementary drive signals to the inputs of the

differential current switches.

The analog and digital sections of the AD9709 have separate

power supply inputs (that is, AVDD and DVDD1/DVDD2) that

can operate independently over a 3.3 V to 5 V range. The digital

section, which is capable of operating up to a 125 MSPS clock

rate, consists of edge-triggered latches and segment decoding

logic circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.20 V band gap

voltage reference, and two reference control amplifiers.