AD9852ASQZ datasheet(24/52 Pages) AD

24 / 52 page

AD9852

Rev. E | Page 24 of 52

supplied or internally generated. See the Internal and External

Update Clock section for a discussion of the I/O update.

Alternatively, the CLR ACC2 control bit (Register Address 1F hex)

is available to clear both the frequency accumulator (ACC1)

and the phase accumulator (ACC2). When this bit is set high,

the output of the phase accumulator results in 0 Hz output from

the DDS. As long as this bit is set high, the frequency and phase

accumulators are cleared, resulting in 0 Hz output. To return to

the previous DDS operation, CLR ACC2 must be set to logic

low. This bit is useful for generating pulsed FM.

Figure 43 graphically illustrates the effect of the CLR ACC2 bit on

the DDS output frequency. Reprogramming the registers while

the CLR ACC2 bit is high allows a new FTW1 frequency and

slope to be loaded.

Another function only available in the chirp mode is the

HOLD pin (Pin 29). This function stops the clock signal to the

ramp rate counter, thereby halting any further clocking pulses

to the frequency accumulator, ACC1.

The effect is to halt the chirp at the frequency existing just

before the HOLD pin is pulled high. When the HOLD pin is

returned low, the clock resumes and chirp continues. During a

hold condition, the user can change the programming registers;

however, the ramp rate counter must resume operation at its

previous rate until a count of 0 is obtained before a new ramp

rate count can be loaded. Figure 44 illustrates the effect of the

hold function on the DDS output frequency.

I/O UD CLK

FREQUENCY

MODE

FTW1

DFW

000 (DEFAULT)

RAMP RATE

011 (CHIRP)

DELTA FREQUENCY WORD

CLR ACC1

Figure 42. Effect of CLR ACC1 in FM Chirp Mode

AD9852ASQZ Folha de dados(PDF) 24 Page - Analog Devices