AD9954SLASHPCBZ datasheet(21/28 Pages) AD

21 / 28 page

AD9951

Rev. A | Page 21 of 28

There are two phases to a communication cycle with the

AD9951. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9951, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9951 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming data

transfer is read or write and the serial address of the register

being accessed.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9951. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9951

and the system controller. The number of bytes transferred

during Phase 2 of the communication cycle is a function of the

Function Register No. 2, which is three bytes wide, Phase 2 requires

that three bytes be transferred. If accessing the frequency tuning

word, which is four bytes wide, Phase 2 requires that four bytes

be transferred. After transferring all data bytes per the instruc-

tion, the communication cycle is completed.

At the completion of any communication cycle, the AD9951

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9951 is registered on the rising edge of

SCLK. All data is driven out of the AD9951 on the falling edge

of SCLK. Figure 21 through Figure 24 are useful in understand-

ing the general operation of the AD9951 serial port.

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 21. Serial Port Write Timing–Clock Stall Low

DON'T CARE

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

DO 5 DO 4 DO 3 DO 2 DO 1

DO 0

DO 7 DO 6

SDO

Figure 22. 3-Wire Serial Port Read Timing–Clock Stall Low

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 23. Serial Port Write Timing–Clock Stall High

DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

DO 7 DO 6

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High

AD9954/PCBZ Folha de dados(PDF) 21 Page - Analog Devices

AD9954/PCBZ Folha de dados(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Folha de dados Download

Ligação URL