ADSP-21486KSWZ-2AB datasheet(28/68 Pages) AD

28 / 68 page

Rev. B

Page 28 of 68

March 2013

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Timer PWM_OUT Cycle Timing

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse-width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Table 25. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

tPWMO

Timer Pulse Width Output

2 × tPCLK – 1.2

2 × (231 – 1) × tPCLK

Figure 12. Timer PWM_OUT Timing

PWM

OUTPUTS

tPWMO

Table 26. Timer Width Capture Timing

Parameter

Min

Max

Unit

Timing Requirement

tPWI

Timer Pulse Width

2 × tPCLK

2 × (231 – 1) × tPCLK

Figure 13. Timer Width Capture Timing

TIMER

CAPTURE

INPUTS

tPWI

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