30F4013 datasheet(19/228 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS70138G-page 19

dsPIC30F3014/4013

2.4

DSP Engine

The DSP engine consists of a high-speed, 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The DSP engine also has the capability to perform

inherent

accumulator-to-accumulator

operations,

which require no additional data. These instructions are

ADD, SUB

and NEG.

The dsPIC30F is a single-cycle instruction flow archi-

tecture, therefore, concurrent operation of the DSP

engine with MCU instruction flow is not possible.

However, some MCU ALU and DSP engine resources

may be used concurrently by the same instruction (e.g.,

, EDAC). (See Table 2-2 for DSP instructions.)

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

Fractional or integer DSP multiply (IF).

Signed or unsigned DSP multiply (US).

Conventional or convergent rounding (RND).

Automatic saturation on/off for AccA (SATA).

Automatic saturation on/off for AccB (SATB).

Automatic saturation on/off for writes to data

memory (SATDW).

Accumulator

Saturation

mode

selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note:

For CORCON layout, see Table 3-3.

TABLE 2-2:

DSP INSTRUCTION

SUMMARY

Instruction

Algebraic

Operation

ACC WB?

CLR

A = 0

Yes

A = (x – y)

EDAC

A = A + (x – y)

MAC

A = A + (x * y)

Yes

MAC

A = A + x2

MOVSAC

No change in A

Yes

MPY

A = x * y

MPY.N

A = – x * y

MSC

A = A – x * y

Yes

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