LPC810M021FN8 datasheet(29/71 Pages) NXP

29 / 71 page

LPC81xM

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Product data sheet

Rev. 3 — 29 July 2013

29 of 71

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

8.23 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The Micro Trace Buffer is implemented on the LPC81xM.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC81xM

is in reset. The JTAG boundary scan pins are selected by hardware when the part is in

boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 4).

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250

s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

Fig 11. Connecting the SWD pins to a standard SWD connector

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