TPS61197

SLVSC25 – JULY 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE

ORDERING PART NUMBER

TOP MARK

-40°C to 85°C

16-Pin SOIC

TPS61197DR

TPS61197

(1)

For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

MIN

MAX

Pin VIN

–0.3

33

Pin FAULT

–0.3

VIN

Pin ISNS, IFB

–0.3

3.3

V

Pin EN, PWM, VDD, GDRV, IDRV

–0.3

20

Pin GDRV 10ns transient

–2.0

20

All other pins

–0.3

7.0

HBM

2

kV

ESD rating

MM

200

V

CDM

1

kV

Continuous power dissipation

See Thermal Information Table

Operating junction temperature range

–40

150

°C

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal

THERMAL INFORMATION

TPS61197

UNITS

SOIC (16 PINS)

Junction-to-ambient thermal resistance

85.8

Junction-to-case (top) thermal resistance

44.5

Junction-to-board thermal resistance

43.3

°C/W

Junction-to-top characterization parameter

13.5

Junction-to-board characterization parameter

42.9

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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