MCR03EZPFX1002 datasheet(18/36 Pages) IRF

18 / 36 page

IR3837MPbF

Rev 1.31

TIMING DIAGRAM OF PGOOD FUNCTIONS

Fig.11 Non-sequence Startup and Vref Margin (Vp =Vcc)

Table 2. The required conditions to achieve simultaneous / ratiometric tracking and sequencing

operations with the circuit configuration of Fig. 8

E/RF >RC/RD

Ramp up from 0V

> 1.5V

Ratiometric Tracking

E/RF =RC/RD

Ramp up from 0V

> 1.5V

Simultaneous Tracking

A/RB >RE/RF > RC/RD

Ramp up from 0V

0.6V

Ratiometric Sequencing

A/RB > RE/RF =RC/RD

Ramp up from 0V

0.6V

Simultaneous Sequencing

> 1.5V

0.6V (Float)

Normal (Non-Sequencing,

Non-Tracking)

Required Condition

Vref (slave)

Operating Mode

E/RF >RC/RD

Ramp up from 0V

> 1.5V

Ratiometric Tracking

E/RF =RC/RD

Ramp up from 0V

> 1.5V

Simultaneous Tracking

A/RB >RE/RF > RC/RD

Ramp up from 0V

0.6V

Ratiometric Sequencing

A/RB > RE/RF =RC/RD

Ramp up from 0V

0.6V

Simultaneous Sequencing

> 1.5V

0.6V (Float)

Normal (Non-Sequencing,

Non-Tracking)

Required Condition

Vref (slave)

Operating Mode

Internal SS

Vref

PGood

256/Fs

0.7V

1.3V

2.0V

SSOK

256/Fs

0.6V

1.15*Vref

0.85*Vref

Power Good Output

The IC continually monitors the output voltage via

Feedback (Fb pin). The feedback voltage is

compared to a threshold. The threshold is set

differently at different operating modes and the

results of the comparison sets the PGood signal.

Figures 11, 12, and 13 show the timing diagram

of the PGood signal at different operating modes.

The PGood pin is open drain and it needs to be

externally pulled high. High state indicates that

output is in regulation.

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