PCMB065T-2R2MS datasheet(15/22 Pages) IRF

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March 27, 2013 | V2.2 | PD97601

IR3473

6A Highly Integrated SupIRBuck

Output Capacitor Selection

Selection of the output capacitor requires meeting

voltage overshoot requirements during load removal, and

meeting steady state output ripple voltage requirements.

The output capacitor is the most expensive converter

component and increases the overall system cost.

The output capacitor decoupling in the converter typically

includes the low frequency capacitor, such as Specialty

Polymer Aluminum, and mid frequency ceramic capacitors.

The first purpose of output capacitors is to provide current

when the load demand exceeds the inductor current,

as shown in Figure 28. Equation 7 shows the charge

requirement for a certain load step. The advantage

provided by the IR3473 at a load step is the reduced delay

compared to a fixed frequency control method. If the

load increases right after the PWM signal goes low, the

longest delay will be equal to the minimum lower gate

on‐time as shown in the Electrical Specifications section.

The IR3473 also reduces the inductor current slew time,

the time it takes for the inductor current to reach equality

with the output current, by increasing the switching

frequency up to 1/(TON + Min Off Time). This results in

reduced recovery time.

Figure 28: Charge Requirement during Load Step

The output voltage drop, VDROP, initially depends on the

characteristic of the output capacitor. VDROP is the sum of

the equivalent series inductance (ESL) of the output

capacitor times the rate of change of the output current

and the ESR times the change of the output current.

VESR is usually much greater than VESL. The IR3473

requires a total ESR such that the ripple voltage at the

FB pin is greater than 7mV.

The second purpose of the output capacitor is to minimize

the overshoot of the output voltage when the load

decreases as shown in Figure 29. By using the law of

energy before and after the load removal, equation 8

shows the output capacitance requirement for a load

step down.

Figure 29: Typical Output Voltage Response Waveform

Boot Capacitor Selection

The boot capacitor starts the cycle fully charged to a

voltage of VB(0). Cg equals 0.58nF in IR3473. Choose a

sufficiently small ΔV such that VB(0)‐ΔV exceeds the

maximum gate threshold voltage to turn on the upper

MOSFET.

Choose a boot capacitor value larger than the calculated

CBOOT in equation 9. Equation 9 is based on charge balance

at CCM operation. Usually the boot capacitor will be

discharged to a much lower voltage when the circuit is

operating in DCM mode at light load, due to much longer

lower MOSFET off time and the bias current drawn by the

IC. Boot capacitance needs to be increased if insufficient

turn‐on of the upper MOSFET is observed at light load,

typically larger than 0.1µF is needed. The voltage rating of

this part needs to be larger than VB(0) plus the desired

derating voltage. It’s ESR and ESL needs to be low in order

to allow it to deliver the large current and di/dt’s which

drive MOSFETs most efficiently. In support of these

requirements a ceramic capacitor should be chosen.

IOUT

ISTEP

VOUT

VESR

VOS

VDROP

(8)

OUT

STEP

OUT

−

⋅

(9)

ΔV

(0)

BOOT

⎟

⎠

⎞

⎜

⎝

⎛

−

⋅

Load

Current

ISTEP

Inductor

Slew

Rate

Output

Charge

Δt

()

(7b)

(7a)

0.5

OUT

STEP

DROP

OUT

STEP

⎥

⎦

⎤

⎢

⎣

⎡

⋅

−

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