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TSU101ILT Folha de dados(PDF) 17 Page - STMicroelectronics |
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TSU101ILT Folha de dados(HTML) 17 Page - STMicroelectronics |
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17 / 33 page ![]() DocID024317 Rev 2 17/33 TSU101, TSU102, TSU104 Application information 33 4 Application information 4.1 Operating voltages The TSU101, TSU102, and TSU104 series of amplifiers can operate from 1.5 V to 5.5 V. Their parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very stable in the full VCC range. Additionally, main specifications are guaranteed on the industrial temperature range from -40 to +85 ° C. 4.2 Rail-to-rail input The TSU101, TSU102, and TSU104 series is built with two complementary PMOS and NMOS input differential pairs. Thus, these devices have a rail-to-rail input, and the input common mode range is extended from VCC- - 0.1 V to VCC+ + 0.1 V. The devices have been designed to prevent phase reversal behavior. 4.3 Input offset voltage drift over temperature The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations. The maximum input voltage drift over temperature is computed in Equation 1. Equation 1 with T = -40 °C and 85 °C. The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 2. ΔVio ΔT ------------ max Vio T () Vio 25° C () – T25 ° C – --------------------------------------------------- = |
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