Data Sheet

ADXL362

Rev. B | Page 35 of 44

SELF TEST REGISTER

Address: 0x2E, Reset: 0x00, Name: SELF_TEST

Refer to the Self Test section for information on the operation of the self test feature, and see the Using Self Test section for guidelines on

how to use this functionality.

Table 19. Bit Descriptions for SELF_TEST

Bits

Bit Name

Settings

Description

Reset

Access

[7:1]

UNUSED

0x0

RW

0

ST

Self Test.

0x0

RW

1 = a self test force is applied to the x-, y-, and z-axes.