AD5452W datasheet(21/24 Pages) AD

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Data Sheet

AD5452W

Rev. 0 | Page 21 of 24

MICROWIRE-to-AD5452W Interface

Figure 46 shows an interface between the DAC and any

MICROWIRE-compatible device. Serial data is shifted out

upon the falling edge of the serial clock, SK, and is clocked into

the DAC input shift register upon the rising edge of SK, which

corresponds to the falling edge of the DAC’s SCLK.

Figure 46. MICROWIRE-to-AD5452W Interface

PIC16C6x/PIC16C7x-to-AD5452W Interface

The PIC16C6x/PIC16C7x synchronous serial port (SSP) is

configured as an SPI master with the clock polarity bit (CKP) = 0.

This is done by writing to the synchronous serial port control

User Manual.

In this example, I/O Port RA1 is used to provide a SYNC signal

and enable the serial port of the DAC. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, two consecutive write operations are

required. Figure 47 shows the connection diagram.

Figure 47. PIC16C6x/7x-to-AD5452W Interface

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which an

AD5452W DAC is mounted should be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. If the DAC is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

These DACs should have ample supply bypassing of 10 µF in

parallel with 0.1 µF on the supply located as close to the package

as possible, ideally right up against the device. The 0.1 µF

capacitor should have low effective series resistance (ESR) and

low effective series inductance (ESI), like the common ceramic

types that provide a low impedance path to ground at high

frequencies, to handle transient currents due to internal logic

switching. Low ESR 1 µF to 10 µF tantalum or electrolytic

capacitors should also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

Components, such as clocks, that produce fast switching signals

should be shielded with a digital ground to avoid radiating noise

to other parts of the board, and they should never be run near

the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A microstrip

technique is the best solution, but its use is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to the ground plane and signal

traces are placed on the solder side.

It is good practice to employ compact, minimum lead length

PCB layout design. Leads to the input should be as short as

possible to minimize IR drops and stray inductance.

The PCB metal traces between VREF and RFB should also be

matched to minimize gain error. To optimize high frequency

performance, the I-to-V amplifier should be located as close to

the device as possible.

SCLK

MICROWIRE*

SYNC

SDIN

AD5452W*

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

SCK/RC3

PIC16C6x/PIC16C7x*

SYNC

RA1

SDIN

SDI/RC4

AD5452W*

*ADDITIONAL PINS OMITTED FOR CLARITY

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