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ADAV4622BSTZ Folha de dados(PDF) 9 Page - Analog Devices

Nome de Peças ADAV4622BSTZ
Descrição Electrónicos  Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder
PDF  28 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADAV4622BSTZ Folha de dados(HTML) 9 Page - Analog Devices

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ADAV4622
Rev. B | Page 9 of
28
TIMING SPECIFICATIONS
Table 2.
Parameter
Description
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
fMCLKI
MCLKI frequency
3.072
24.576
MHz
tMCH
MCLKI high
10
ns
tMCL
MCLKI low
10
ns
tRESET
RESET low
200
ns
MASTER CLOCK OUTPUT
tJIT
Period jitter
800
ps
tCH
MCLK_OUT high
45
55
%
tCL
MCLK_OUT low
45
55
%
I2C PORT
fSCL
SCL clock frequency
400
kHz
tSCLH
SCL high
600
ns
tSCLL
SCL low
1.3
μs
Start Condition
tSCS
Setup time
600
ns
Relevant for repeated start condition
tSCH
Hold time
600
ns
After this period, the first clock is generated
tDS
Data setup time
100
ns
tSCR
SCL rise time
300
ns
tSCF
SCL fall time
300
ns
tSDR
SDA rise time
300
ns
tSDF
SDA fall time
300
ns
Stop Condition
tSCS
Setup time
0
ns
SERIAL PORTS
Slave Mode
tSBH
BCLK high
40
ns
tSBL
BCLK low
40
ns
fSBF
BCLK frequency
64 × fS
tSLS
LRCLK setup
10
ns
To BCLK rising edge
tSLH
LRCLK hold
10
ns
From BCLK rising edge
tSDS
SDIN setup
10
ns
To BCLK rising edge
tSDH
SDIN hold
10
ns
From BCLK rising edge
tSDD
SDO delay
50
ns
From BCLK falling edge
Master Mode
tMLD
LRCLK delay
25
ns
From BCLK falling edge
tMDD
SDO delay
15
ns
From BCLK falling edge
tMDS
SDIN setup
10
ns
From BCLK rising edge
tMDH
SDIN hold
10
ns
From BCLK rising edge



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