1.

General description

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type

flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q

output.

The master reset (MR) is an asynchronous active LOW input and operates independently

of the clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2.

Features and benefits



24 mA output drive (V

40 Cto+85 C and 40 Cto+125 C.

74LVC1G175

Single D-type flip-flop with reset; positive-edge trigger

Rev. 5 — 6 December 2011

Product data sheet