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Copyright © 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispLEVER, ispLeverCORE, Lattice Diamond, LatticeCORE,

LatticeECP3, LatticeECP2M, LatticeMico32, sysCLOCK, sysCONFIG, sysDSP, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United

States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

May 2012

Order #: I0198H

Design Made Simple with Advanced Design Software and IP

Lattice Diamond Design Software

implementation tools optimized for cost sensitive, low-power Lattice

FPGA architectures. Diamond is the next generation replacement

design flow, and numerous other enhancements. The combination

of new and enhanced features allows users to complete designs

faster, easier, and with better results than ever before.

Intellectual Property

support the easy integration of commonly used functions. Lattice

also offers IP Suites that are a collection of related IP cores for

select applications/markets at very attractive prices. The following

table provides a partial listing of IP Suites available for the

LatticeECP3 family. In addition to these, LatticeCORE Connections

Partners also offer a wide range of IP. For a complete list of IP

options, please visit www.latticesemi.com/ip.

LatticeCORE IP Suites for LatticeECP3 FPGAs

IP Suite

Included IP Cores

Value

• DDR3/DDR2/DDR Memory

Controller

• FFT Compiler

• FIR Filter Generator

• Triple Speed 10/100/1G

Ethernet MAC

PCI

Express

• PCI Express Endpoint x1 / x4

• PCI Express Root Complex

Lite x1 / x4

• PCI Target 32-bit / 64-bit

• PCI Master/Target 32-bit /

64-bit

• Scatter Gather DMA

Gigbit

Ethernet

• 10Gb+ Ethernet MAC

• Scatter Gather DMA

• SGMII & Gigabit Ethernet

MAC

• Triple Speed 10/100/1G

Ethernet MAC

• XAUI

Signal

Processing

• Advanced FIR Filter

• Block Convolutional Encoder

• Block Viterbi Decoder

• Cascaded Integrated Comb

Filter - CIC

• CORDIC

• Correlator

• Distributed Arithmetic FIR

Filter

• Dynamic Block Reed Solomon

Decoder / Encoder

• FFT Compiler

• FIR Filter Generator

• Interleaver / De-interleaver

• Numerically Controlled

Oscillator

• Turbo Decoder / Encoder

Video &

Display

• 2D FIR Filter

• Color Space Converter

• Edge Detector

• Gamma Corrector

• Median Filter

• Tri-rate SDI PHY

• Scaler

LatticeECP3 (Economy Plus FPGAs with SERDES, sysDSP Blocks, & Source Synchronous I/O)

Parameter

ECP3-17

ECP3-35

ECP3-70

ECP3-95

ECP3-150

LUTs (K)

17

33

67

92

149

Number of EBR SRAM Blocks

38

72

240

240

372

EBR Block SRAM (K bits)

700

1327

4420

4420

6850

Distributed RAM (K bits)

36

68

145

188

303

18x18 Embedded Multipliers

24

64

128

128

320

3.2Gbps SERDES Channels

4

4

12

12

16

Maximum Available I/O

222

310

490

490

586

Number of PLLs/DLLs

2+2

4+2

10+2

10+2

10+2

-S, -L

-S, -L

-S, -L

-S, -L

-S, -L

-6, -7, -8

-6, -7, -8, -9

-6, -7, -8, -9

-6, -7, -8, -9

-6, -7, -8, -9

Packages & SERDES / I/O Combinations

328-ball csBGA (10 x 10 mm)

2/116

256-ball ftBGA (17 x 17 mm)

4/133

4/133

484-ball fpBGA (23 x 23 mm)

4/222

4/295

4/295

4/295

672-ball fpBGA (27 x 27 mm)

4/310

8/380

8/380

8/380

1156-ball fpBGA (35 x 35 mm)

12/490

12/490

16/586

1. -S = Standard Power; -L = Low Power

2. -9 = High-Speed Device