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1337CSRI Folha de dados(PDF) 14 Page - Integrated Device Technology |
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1337CSRI Folha de dados(HTML) 14 Page - Integrated Device Technology |
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14 / 24 page ![]() IDT1337 REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE 14 IDT1337 REV J 111009 Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: SCL only. Note 3: SDA, INTA, and SQW/INTB. Note 4: ICCA—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC. Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC. Note 6: SQW enabled. Note 7: Specified with the SQW function disabled by setting INTCN = 1. Note 8: Using recommended crystal on X1 and X2. Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC < 1.8 V. Note 10: After this period, the first clock pulse is generated. Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released. Note 14: CB—total capacitance of one bus line in pF. Note 15: Guaranteed by design. Not production tested. Rise Time of Both SDA and SCL Signals, Note 14 tR Fast Mode 20 + 0.1CB 300 ns Standard Mode 20 + 0.1CB 1000 Fall Time of Both SDA and SCL Signals, Note 14 tF Fast Mode 20 + 0.1CB 300 ns Standard Mode 20 + 0.1CB 300 Setup Time for STOP Condition tSU:STO Fast Mode 0.6 µs Standard Mode 4.0 Capacitive Load for Each Bus Line, Note 14 CB 400 pF I/O Capacitance (SDA, SCL) CI/O Note 15 10 pF 32.768 kHz Clock Accuracy with External Crystal TA=25°C VCC=3.3 V ±10 ppm 32.768 kHz Clock Accuracy with Internal Crystal TA=25°C VCC=3.3 V (crystal accuracy ±20ppm) ±30 ppm Parameter Symbol Conditions Min. Typ. Max. Units |
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